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14-bit, 250 ksps pulsar? adc in msop/qfn prelim inary technical data AD7942 rev pr b in fo rmation furn is h e d by an al o g dev i ces is believed to be a ccu rate and r e liable. how e ver, no r e spons i bili ty is assumed by analog devices fo r its use, nor f o r an y i n fri n geme nt s of p a t e nt s or ot her ri g h t s o f th ird parties th at may result fro m its use . specifications subject to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot he rwi s e un der a n y p a t e nt or p a t e nt r i ghts of anal og de vices. trad emarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures 14-bit resolut i on with no missing codes throughput: 250 ksps inl: 0.4 lsb t y p, 1 lsb max (0.0 061 % of fsr) s/(n + d): 85 d b @ 20 khz thd: ?100 db @ 20 kh z pseudo- d iffere ntial analog in put range 0 v to v re f with v re f up to vd d n o pipeline delay single-supply 5v operation with 1.8 v/2.5 v/3 v/5 v logic interf ace serial interf ace spi?/qspi?/wire/dsp compatible daisy chain multiple adcs an d busy indicato r power dissipati o n 1.15 mw @ 2.5 v/100 ks ps, 3. 3 mw @ 5 v/10 0 ksps, 1.15 w @ 2. 5 v/100 sps stand-by curr e n t: 1 na 10-lea d packag e: msop (msop-8 si ze) an d 3 mm 3 mm qfn (lfcsp) (s ot-23 size) pin-for-pin compatible with t h e 16-bit ad76 85 applic a t io ns battery-powered eq uipment data acq u isitio n instrumentation medical instr u ments process control table 1. msop , qfn (lfcsp)/sot-23 1 4 and16-bit adc type 100 ksps 250 ksps 500 ksps 16-bit true differential ad7684 ad7687 ad7688 16-bit pseudo differential/uni polar ad7683 ad7685 ad7694 ad7686 16-bit unipol ar ad7680 14-bit pseudo differential/uni polar AD7942 ad7946 14-bit unipol ar ad7940 applic a t io n di a g r a m AD7942 ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8 t o vdd 3- or 4-wire interf ace (spi, daisy chain, cs) 0.5 t o 5v 2.5v to 5v 0 t o vref fi g u r e 1 . gener a l description the AD7942 is a 14-b i t, c h a r g e r e dis t r i b u tio n succes si v e ap p r ox i m at i o n , a n a l o g - t o - d i g i t a l c o n v e r t e r ( a d c ) t h at o p e r at e s f r om a s i ng l e 5 v p o we r su p p ly , v d d . i t c o n t ai ns a l o w p o we r , h i g h s p e e d, 1 4 - b i t s a m p l i ng a d c w i t h no m i s s i ng c o d e s , a n in t e r n a l con v ers i o n clo c k, and a vers a t i l e s e r i a l i n t e r f ace p o r t . the p a r t a l s o co n t a i n s a lo w n o i s e, wi de b a ndwi d t h , sh o r t a p er t u r e d e l a y t r ack-and- h o ld c i r c ui t. on t h e c n v r i sin g e d ge, i t s a m p les a n ana l og in p u t i n + b e tw e e n 0 v t o ref wi t h r e sp e c t to a g r o u nd s e ns e in?. t h e r e fe r e n c e vol t a g e, r e f , is a p plie d ex ter n a l ly a n d c a n b e s e t u p to t h e su p p ly vol t a g e. it s p o w e r s c a l e s l i n e a r l y w i t h t h r o u g h p u t . the s p i com p a t i b le s e r i al i n t e r f ace als o fe a t ur es t h e ab i l i t y , usin g t h e s d i in p u t, t o d a isy chain s e v e ra l a d cs o n a sin g le 3 - wir e b u s an d p r o v ides a n op t i ona l b u s y i ndic a to r . i t is co m p a t i b le wi th 1.8 v , 2.5 v , 3 v , o r 5 v log i c u s in g th e s e p a ra te su p p ly v i o . the AD7942 is h o us e d in a 10-l e ad mso p o r a 10-lead q f n (lfcs p ) wi th op era t ion s p ecif ied f r o m ?40c t o +85c.
AD7942 preliminary technical data rev pr b | page 2 of 28 table of contents specifications..................................................................................... 3 timing specifications....................................................................... 5 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 terminology ...................................................................................... 9 typical performance characteristics ........................................... 10 circuit information.................................................................... 13 converter operation.................................................................. 13 typical connection diagram ................................................... 14 digital interface .......................................................................... 18 application hints ........................................................................... 25 layout .......................................................................................... 25 evaluating the AD7942s performance .................................... 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 27 revision history 8/04revision b: preliminary
preliminary technical data AD7942 rev pr b | page 3 of 28 specifications vdd = 2.3 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, t a = C40c to +85c, unless otherwise noted. table 2. parameter conditions min typ max unit resolution 14 bits analog input voltage range in+ ? in? 0 v ref v absolute input voltage in+ ?0.1 vdd + 0.1 v in? ?0.1 0.1 v analog input cmrr f in = 250 khz 65 db leakage current at 25c acquisition phase 1 na input impedance see the analog input section. accuracy no missing codes 14 bits differential linearity error ?0.7 0.25 +0.7 lsb 1 integral linearity error ?1 0.4 +1 lsb transition noise ref = vdd = 5 v 0.33 lsb gain error 2 , t min to t max tbd tbd lsb gain error temperature drift tbd ppm/c offset error 2 , t min to t max tbd tbd mv offset temperature drift tbd ppm/c power supply sensitivity vdd = 5v 5% tbd lsb throughput conversion rate vdd = 4.5 v to 5.5 v 0 250 ksps vdd = 2.3 v to 4.5 v 0 200 ksps transient response full-scale step 1.8 s ac accuracy signal-to-noise f in = 20 khz, v ref = 5 v 83 85 db 3 f in = 20 khz, v ref = 2.5 v 84 db spurious-free dynamic range f in = 20 khz ?100 db total harmonic distortion f in = 20 khz ?100 db signal-to-(noise + distortion) f in = 20 khz, v ref = 5 v 83 85 db f in = 20 khz, v ref = 5 v, ?60 db input 25 db f in = 20 khz, v ref = 2.5 v 84 db intermodulation distortion 4 tbd db 1 lsb means least significant bit. with the 5 v input range, one lsb is 305.2 v. 2 see section. these specificat ions do include full temperature range variation but do not include the error contrib ution from the external reference. terminology 3 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale, unless otherwise specified. 4 f in1 = 21.4 khz, f in2 = 18.9 khz, each tone at ?7 db below full-scale.
AD7942 preliminary technical data rev pr b | page 4 of 28 parameter conditions min typ max unit vdd = 2.3 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, t a = C40c to +85c, unless otherwise noted. table 3. reference voltage range 0.5 vdd + 0.3 v load current 250 ksps, ref = 5 v tbd a sampling dynamics ?3 db input bandwidth 2 mhz aperture delay vdd = 5 v 2.5 ns digital inputs logic levels v il C0.3 0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 14 bits straight binary pipeline delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 2.3 5.5 v vio specified performance 2.3 vdd + 0.3 v vio range 1.8 vdd + 0.3 v standby current 1, 2 vdd and vio = 5 v, 25c 1 50 na power dissipation vdd = 2.5 v, 100 sps throughput 1.15 w vdd = 2.5 v, 100 ksps throughput 1.15 2 mw vdd = 2.5 v, 200 ksps throughput 2.25 4 mw vdd = 5 v, 100 ksps throughput 3.3 5 mw vdd = 5 v, 250 ksps throughput 12.5 mw temperature range 3 specified performance t min to t max ?40 +85 c 1 with all digital inputs forced to vio or gnd as required. 2 during acquisition phase. 3 contact analog devices for extended temperature range.
preliminary technical data AD7942 rev pr b | page 5 of 28 timing specifications ?40c to +85c, vio = 2.3 v to 5.5 v or vdd + 0.3 v, whichever is the lowest, unless otherwise stated. table 4. vdd = 4.5 v to 5.5 v 1 symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 2.2 s acquisition time t acq 1.8 s time between conversions t cyc 4 s cnv pulse width ( cs mode ) t cnvh 10 ns sck period ( cs mode ) t sck 15 ns sck period ( chain mode ) t sck vio above 4.5 v 19 ns vio above 3 v 20 ns vio above 2.7 v 21 ns vio above 2.3 v 22 ns sck low time t sckl 7 ns sck high time t sckh 7 ns sck falling edge to data remains valid t hsdo 5 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 14 ns vio above 3 v 15 ns vio above 2.7 v 16 ns vio above 2.3 v 17 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 4.5 v 15 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 15 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 5 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 4 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi vio above 4.5 v 15 ns vio above 2.3 v 26 ns 1 see error! reference source not found. and error! reference source not found. for load conditions.
AD7942 preliminary technical data rev pr b | page 6 of 28 ?40c to +85c, vio = 2.3 v to 4.5 v or vdd + 0.3 v, whichever is the lowest, unless otherwise stated. table 5. vdd = 2.3v to 4.5 v 1 symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.7 3.2 s acquisition time t acq 1.8 s time between conversions t cyc 5 s cnv pulse width ( cs mode ) t cnvh 10 ns sck period ( cs mode ) t sck 25 ns sck period ( chain mode ) t sck vio above 3 v 29 ns vio above 2.7 v 35 ns vio above 2.3 v 40 ns sck low time t sckl 12 ns sck high time t sckh 12 ns sck falling edge to data remains valid t hsdo 5 ns sck falling edge to data valid delay t dsdo vio above 3 v 24 ns vio above 2.7 v 30 ns vio above 2.3 v 35 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 30 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 8 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 5 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 4 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi 26 ns 1 see error! reference source not found. and error! reference source not found. for load conditions.
prelim inary technical data AD7942 r e v pr b | pa ge 7 o f 28 absolute maximum ra tings table 6. p a r a m e t e r r a t i n g analog inputs in+ 3 , in? 1 , ref gnd ? 0.3 v to vdd + 0.3 v or 130 ma supply voltages vdd, vio to g n d ?0.3 v to +7 v vdd to vio 7 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction tempe r ature 150c ja thermal impedance 200c/w (msop -10) jc thermal impedance 44c/w (msop- 10) lead temperature range vapor phase (60 sec) 215c infrared (15 sec) 220c 3 s e e the a n al o g input s e ctio n. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. 500 ai ol 500 ai oh 1.4v to sdo c l 50pf 02968-p r h-002 f i gure 2 . l o a d cir c ui t fo r di g i ta l inter f a c e t i mi ng 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t delay notes 1. 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2. 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. 02968-p r h-003 f i gure 3. v o ltag e r e ferenc e l e vels fo r t i ming
AD7942 prelim inary technical data r e v pr b | pa ge 8 o f 28 pin conf igura t ion and fu nction descriptions AD7942 ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 f i gure 4.10-l ead m s op and qfn (lf c sp ) p i n configur ation ta ble 7. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic type 1 function 1 r e f a i reference input voltage. the ref range is from 0.5 v to vdd. it i s referre d to the gnd pin. t h is pin should be decoupled closely to the pin with a 10 f capacitor. 2 v d d p p o w e r s u p p l y . 3 i n + a i analog input. it is referred to in in?. the voltage range, i.e., the difference betwee n in+ and in?, is 0 v to v ref . 4 in? ai analog input ground sense. to be connected t o the anal og ground plane or t o a remote sen s e ground. 5 gnd p power supply g r ound. 6 c n v d i convert input. t h is input has multip le functions. on its leading edge, it initiates the conversi ons and selects the inter f ace mod e of the part, chain or cs mode. in cs mod e , it enables the s d o pin whe n lo w. in chain mod e , the d a ta should be read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchro n ized to sck. 8 sck di serial data clock input. when the part is se lect ed , the conversi on result is shift e d out by this cl ock. 9 sdi di serial data inpu t. this input provid es multiple f e atures. it selects th e interface mode of the ad c as follows: chain mode is selected if sdi is low during the cnv risi ng edge. in this mode, sdi is used as a data input to daisy chain the conver sion re sults of two or mor e adcs onto a si ngle sdo line. t h e digital data level on sdi is output on sdo with a delay of 14 sck cycles. cs mode is selecte d if sdi is high during the cnv ri si ng edge. in this mode, either sdi or cnv can enable the serial outpu t signals w h en l o w, and if sdi or c nv is low whe n the conversi o n is comp lete, the busy indicator feature is enabled. 1 0 v i o p input/ output in terface digital power. no min ally at the same supply as the host i n terface ( 1 .8 v, 2.5 v, 3 v, or 5 v). 1 a i = a n al og i n put, di = digital i n put, d o = digital o u tput, and p = p o w e r
prelim inary technical data AD7942 r e v pr b | pa ge 9 o f 28 terminology i n t e g r a l n o nlin ea ri ty e r r o r (inl) li n e a r i t y e r r o r r e f e r s t o th e devia t i o n o f ea ch in d i v i d u al code f r o m a line dr a w n f r o m nega t i ve f u l l s c a l e t h ro ug h p o si t i ve f u l l scale . th e po i n t used a s n e ga ti v e full scale occur s 1/ 2 l s b b e f o r e th e f i r s t co d e tra n si ti o n . p o si ti v e full scale i s d e f i n e d a s a lev e l 1 1/ 2 l s b bey o n d th e la s t cod e tra n si ti o n . th e de vi a t i o n i s m e as ur ed f r o m th e middle o f eac h co de t o th e t r ue s t ra ig h t lin e (f igur e 21). d i f f erenti a l n o n l i n e a r i ty e r ror ( d n l ) i n a n i d e a l a d c , c o d e t r ans i t i ons are 1 l s b a p ar t . dn l i s t h e maxim u m d e v i a t io n f r o m t h i s i d e a l va l u e . i t is o f t e n sp e c if ie d i n te r m s of re s o lut i on for w h i c h n o m i ss i n g c o d e s are g u ar an te e d . off s et e r r o r the f i rs t tra n si t i o n sh o u ld o c c u r a t a le ve l 1/2 l s b a b o v e a n alo g g r o u n d (152.6 v f o r th e 0 v t o 5 v ra n g e). th e o f fs et er r o r is th e de vi a t i o n o f th e a c t u al tra n si ti o n f r o m tha t po i n t . ga in er r o r the las t tra n s i tio n (f r o m 111 . . . 10 t o 111 . . . 11 ) s h o u ld o c c u r for an an a l o g volt age 1 1 / 2 l s b b e l o w t h e nom i n a l f u l l s c a l e (4.999542 v f o r th e 0 v t o 5 v r a n g e). th e ga in er r o r is th e d e vi a t i o n o f th e a c t u al lev e l o f t h e la s t tra n si ti o n f r o m th e i d eal le v e l a f t e r t h e o f fs et has b e en ad j u s t e d o u t. s p uri o us-f r e e d y na mi c r a n g e (s fd r) the dif f er ence , i n de c i b e ls (db), b e tw e e n t h e r m s a m pli t ude o f t h e i n p u t sig n al a nd t h e p e a k s p ur io us sig n al . e f f e c t iv e n u mb er of b i ts (eno b) en o b is a m e asur em en t o f t h e r e s o l u t i o n wi t h a sine w a v e in p u t. i t is r e l a t e d t o s/(n+ d ) b y t h e fol l o w in g fo r m u l a [ ] ( ) 02 . 6 / 76 . 1 d n / s enob ? + = db a nd is ex p r ess e d in b i ts. t o t a l ha r m on i c d i s t or t i on ( t h d ) t h d i s t h e ra tio o f th e rm s s u m o f th e f i r s t f i v e h a rm o n i c co m p on e n ts t o t h e r m s val u e o f a f u l l -s cale in pu t sig n al an d is exp r es s e d i n db . s i g n a l -t o-n o is e r a ti o (s nr) s n r is t h e r a t i o o f t h e r m s val u e o f t h e ac t u al in p u t sig n al t o t h e r m s su m of a l l ot he r sp e c t r a l c o m p o n e n t s b e l o w t h e n y qu i s t f r e q uen c y , excl udin g ha r m o n ics a nd dc. t h e va lue fo r s n r is exp r es s e d i n db . s i g n a l -t o-(n o i s e + dis t o r t i o n ) r a t i o (s/[ n+d] ) s/(n+d) is t h e ra t i o o f t h e r m s val u e o f t h e ac t u al in p u t sig n al t o th e rm s s u m o f all o t h e r s p ec tral co m p o n en ts be lo w t h e n y q u ist f r e q ue nc y , in cl udi n g har m o n ics b u t excl udin g dc. the val u e fo r s/(n+d) is exp r es s e d in db . ap e r t u r e d e l a y a p er t u r e del a y i s a m e asur e o f t h e ac q u isi t ion p e r f o r ma n c e and i s th e tim e be t w ee n t h e ri si n g e d g e o f th e c n v i n p u t a n d w h en t h e i n p u t sig n al is h e l d fo r a co n v ersio n . t r ansi en t resp o n s e the t i m e r e q u ir e d fo r t h e ad c t o acc u ra t e l y ac q u ir e i t s in pu t a f t e r a full - s c a l e s t e p fu n c ti o n wa s a p p l ied .
AD7942 prelim inary technical data r e v pr b | pa ge 10 o f 28 typical perf orm ance cha r acte ristics f i gure 5 . integr a l no nli n ea ri t y vs . c o d e f i g u re 6. his t og r a m of a dc input at t h e cod e ce nte r f i g u re 7. fft plot f i gur e 8 . d i ffe r e ntia l no nl inea ri t y vs . c o de f i g u re 9. his t og r a m of a dc input at t h e cod e ce nte r fi g u r e 1 0 . s / [ n + d ] v s . fr e q u e n c y
prelim inary technical data AD7942 r e v pr b | pa ge 11 o f 28 f i g u re 11. snr v s . t e mper at ur e f i g u re 12. th d v s . f r equ e nc y f i g u re 13. thd , sf dr v s . t e mper at ur e f i gure 14. snr and thd vs . input l e v e l f i gure 15. o p er atin g currents v s . sup p l y f i gure 16. p o wer - d o wn cur r ents vs. t e mp e r atu r e
AD7942 prelim inary technical data r e v pr b | pa ge 12 o f 28 f i gure 17. o p er atin g currents v s . t e mper atu r e f i gure 18. o ffs et a n d g a in e r r o r v s . t e mpe r atu r e f i g u re 19. t dsdo vs . c a pac i tanc e l o ad and su p p ly
prelim inary technical data AD7942 r e v pr b | pa ge 13 o f 28 sw+ msb 4,096c in+ lsb comp control logic switches control busy output code cnv ref gnd in? 4c 2c c c 8,192c sw? msb 4,096c lsb 4c 2c c c 8,192c f i gur e 2 0 . adc simpl i f ie d s c hema ti c circuit informa t ion the AD7942 is a fast, lo w p o w e r , sin g le-s u p p l y , p r ecis e 14-b i t ad c usin g a su ccessi v e a p p r o x i m a t ion a r chi t e c t u r e . the AD7942 is ca p a b l e o f con v er tin g 250,000 s a m p les p e r s e con d (250 ks ps) a nd p o w e rs do wn betw een c o n v ersio n s. w h en o p era t ing a t 100 s p s, f o r exa m p l e , i t co ns um es typ i c a l l y 1.15w wi t h a 2.5v s u p p l y , ide a l f o r ba t t er y-p o w e r e d ap p l i c at i o n s . the AD7942 p r o v ides the us er wi t h an o n -c hi p trac k-and-h o ld a nd do es n o t ex hib i t an y p i p e li n e d e l a y o r la te n c y , ma k i ng i t ide a l f o r m u l t i p l e m u l t i p lexe d c h a n n e l a p p l ic a t io n s . the AD7942 is s p ecif ie d f r o m 2.3 v t o 5.5 v , a nd can be in t e r f ace d t o ei t h er 5 v , 3.3 v , 2. 5 v , o r 1.8 v dig i tal log i c. i t is h o us e d in a 10-l e ad msop o r a t i n y 10-le a d qfn (lfcs p ) t h a t co m b i n es sp a c e s a v i n g s and a l lo ws f l ex i b le co nf i g ur a t io n s . i t i s pi n - f o r - pi n - c o m p a t i b l e w i t h t h e 1 6 b i t a d c ad7685 . c o nverter oper a t ion the AD7942 is a s u cces si v e a p p r o x ima t ion ad c bas e d o n a ch ar ge re d i st r i but i on d a c . f i g u re 2 0 show s t h e s i m p l i f i e d s c h e ma t i c o f t h e ad c. th e c a p a ci t i v e d a c con s is ts o f tw o iden t i ca l a r ra y s o f 14 b i na r y w e ig h t e d c a p a ci t o rs, w h ich a r e co nnec t e d t o t h e tw o co m p a r a t o r in p u ts. duri n g th e a c q u i s i t i o n p h ase , t e rm i n als o f th e a r ra y ti ed t o th e c o m p ar a t or s i n put are c o n n e c t e d to g n d v i a s w + a n d s w ? . all i n de pen d en t s w i t ch e s a r e co n n ec t e d t o th e a n al og i n p u ts . t h us, the ca p a ci t o r a r ra ys a r e used as sam p lin g ca p a ci t o r s an d acq u ir e t h e a n al og sig n al o n t h e in+ an d i n ? i n p u ts. w h e n t h e acq u isi t ion pha s e is co m p lete and t h e cn v i n pu t go es hig h , a co n v ersio n phas e is ini t i a t e d . w h e n t h e con v ersio n phas e beg i n s , sw+ and sw? a r e op ened f i rs t. th e two ca p a ci t o r a r r a y s a r e t h en dis c o n n e c t e d f r o m t h e i n p u ts and co n n e c te d to t h e g n d i n p u t. ther efo r e , t h e dif f er en t i al v o l t ag e b e tw e e n t h e in p u ts in+ and in? ca p t ur e d a t th e end o f th e acq u isi t io n phas e is a p plie d t o t h e com p a r a t o r in p u ts, ca usi n g t h e co m p a r a t o r t o b e co m e un bala n c ed . b y s w i t ch i n g ea c h e l em en t o f t h e c a p a ci to r a r r a y b e twe e n gnd and ref , t h e com p a r a t o r i n pu t v a r i e s by bi n a r y w e i g ht e d v o lt a g e s t e p s ( v ref /2, v ref / 4 . . . v ref /16384). the co n t r o l log i c t o g g l es th es e s w i t c h es, sta r tin g wi t h t h e ms b , in o r der t o b r in g th e com p a r a t o r bac k in t o a bala n c e d co n d i t i o n . a f t e r t h e co m p le ti o n o f th i s p r oce s s, th e p a r t r e t u r n s t o t h e ac q u isi t ion phas e and t h e con t r o l log i c gen e r a tes t h e a d c o u tp u t co de a nd a b u s y sig n a l indic a to r . b e ca us e the AD7942 has a n on-bo a r d con v ersion c l o c k, t h e s e r i al c l o c k, sc k, is n o t r e q u ir e d f o r th e con v ersio n p r o c es s.
AD7942 prelim inary technical data r e v pr b | pa ge 14 o f 28 tra n sfer f u nctions the ideal tran sf er c h a r ac t e r i s t ic f o r th e AD7942 is s h o w n in f i gur e 21 a nd t a b l e 8. 000...000 000...001 000...010 111...101 111...110 111...111 adc code (s traight binary ) analog input +fs ? 1.5 lsb + f s ? 1 lsb ?fs + 1 lsb ?f s ?fs + 0.5 lsb 02968-p r h-006 f i g u re 21. a d c ide a l t r ans f er f u nc t i o n ta ble 8. out p ut codes a n d i d ea l input volt a g es description analo g input v re f = 5 v digital o u tput co de hexa fsr C 1 lsb 4.999695 v 3fff 4 midscale + 1 lsb 2.500305 v 2001 midscale 2.5 v 2000 midscale C 1 lsb 2.499695 v 1fff Cfsr + 1 lsb 305.2 v 0001 Cfsr 0 v 0000 5 4 this is al so the c o de for an overranged anal og input ( v in + C v in ? above v re f C v gnd ). 5 this is al so the c o de for an un d e rranged anal og input ( v in + C v in ? below v gnd ). t y p i c a l c o nnec t i o n di a g r a m f i gur e 22 s h o w s a n exa m p l e o f t h e r e comm en de d co nn ec tion dia g ra m f o r the AD7942 w h en m u l t i p le s u p p lies a r e a v a i la b l e. AD7942 ref gnd vdd in? in+ vio sdi sck sdo cnv 3- or 4-wire interf ace (note 5) 100nf 100nf 5v 10 f (note 2) 1.8v t o vdd ref 0 t o vref 33 ? 2.7nf (note 3) (note 4) (note 1) note 1: see reference section for reference selection. note 2: c ref is usuall y note 3: see driver amplifier choice section. note 4: optional fil ter. see analog input section. note 5: see digit al interf ace for most convenient interf ace mode. a 1 0 f ceramic cap acit or (x5r). f i g u re 22. t y pic a l a p pli c at ion d i ag r a m w i t h m u lt ipl e s u p p li es
prelim inary technical data AD7942 r e v pr b | pa ge 15 o f 28 an a l og i n pu t f i g u re 2 3 show s an e q u i v a l e n t c i rc u i t of t h e i n put st r u c t u r e of th e AD7942. the tw o dio d es, d1 a nd d2, p r o v ide e s d p r o t e c t i o n fo r t h e a n alog in p u ts in+ an d i n ?. c a r e m u s t be ta k e n t o en s u r e tha t t h e a n alog in p u t sig n al ne v e r exce e d s t h e s u p p l y ra i l s b y m o r e t h a n 0.3 v b e c a us e t h is wi l l ca u s e t h es e dio d es t o b e come fo r w a r d-b i as e d a nd st a r t co nd u c t i n g c u r r en t. h o w e ver , t h es e dio d es c a n handle a f o r w a r d-b i as ed c u r r en t o f 130 ma maxim u m. f o r in s t an c e , t h es e c o n d i t io ns co u l d e v en t u al l y o c c u r w h e n t h e in p u t b u f f er s (u1) s u p p lies a r e dif f er en t f r o m vd d . i n such a cas e , an i n p u t b u f f er wi t h a sh or t-cir c ui t c u r r e n t limi t a tion can b e us ed t o p r o t ec t th e p a r t . c in r in d1 d2 c pin in+ or in? gnd vdd f i g u re 23. equiv a le nt a n al og input c i rcuit this a n alog in pu t s t r u c t ur e al lo ws t h e s a m p l i n g o f t h e dif f er en tial sig n al betw een in+ a nd in?. b y usin g this d i f f er en ti al i n p u t , sm all si gn als co m m o n t o bo th i n p u ts a r e re j e c t e d , a s s h ow n i n fi g u re 2 4 , w h i c h re pre s e n t s t h e t y pi c a l cmrr o v er f r eq uen c y . f o r in s t a n c e , b y usin g in? t o s e n s e a r e m o t e s i gnal gr o u n d , gr o u n d p o t e n t i a l di f f e r e n c e s bet w een th e s e n s o r an d t h e l o ca l a d c g r o u nd a r e eli m in a t e d . fi g u r e 2 4 . a n a l o g i n p u t c m r r v s . fr e q u e n c y d u r i n g t h e ac quisi t io n phas e , t h e i m p e dan c e of t h e a n alog in p u t in+ c a n b e m o dele d as a p a r a l l el co m b in a t io n o f ca p a c i t o r c pi n a n d th e n e t w o r k f o rm ed b y th e s e ri e s co n n ecti o n of r in a nd c in . c pi n is p r ima r i l y t h e p i n c a p a c i t a n c e . r in is typ i cal l y 3 k? and is a l u m p e d co m p on en t made u p o f s o me s e r i al r e sis t o r s and the o n r e sis t a n c e o f th e s w i t c h es. c in is typ i cal l y 30 pf a nd is ma inl y the ad c s a m p l i ng ca p a c i t o r . d u r i n g t h e con v ersio n phas e , w h er e t h e s w i t ch es a r e o p e n e d , t h e i n p u t im p e da n c e is limi t e d to c pi n . r in a nd c in ma k e a 1- p o le , lo w-p a s s f i l t er tha t r e d u ces un desira b l e aliasin g ef f e c t an d limi ts t h e n o is e . w h en t h e s o ur c e im p e dan c e o f t h e dr ivin g cir c ui t is lo w , t h e AD7942 can be dr i v en dir e c t l y . l a rg e s o ur ce im p e dan c es si gn i f i c a n tl y a f f e ct th e a c pe rf o r m a n c e , e s peci ally t o tal h a r m on i c d i stor t i on ( t h d ) . t h e d c p e r f or m a n c e s are l e ss s e n s i t i v e t o t h e i n p u t i m p e dan c e . the maxi m u m s o ur ce i m pe d a n c e d e pe n d s o n th e a m o u n t o f t h d t h a t c a n b e t o lera t e d . t h e t h d deg r ades as a f u n c t i on o f t h e s o ur ce im p e d a n c e and t h e max i m u m i n p u t f r e q ue n c y , as sh o w n in f i gur e 25. f i g u re 25. th d v s . a n al og input f r equ e nc y and s o urc e r e s i s t anc e
AD7942 preliminary technical data rev pr b | page 16 of 28 driver amplifier choice although the AD7942 is easy to drive, the driver amplifier needs to meet the following requirements: the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the AD7942. note that the AD7942 has a noise much lower than most of the other 14- bit adcs and, therefore, can be driven by a noisier op amp while preserving the same or better system performance. the noise coming from the driver is filtered by the AD7942 analog input circuit 1-pole, low-pass filter made by r1 and c2 or by the external filter, if one is used. ? for ac applications, the driver needs to have a thd performance suitable to that of the AD7942. figure 12 gives the thd versus frequency that the driver should exceed. ? for multichannel multiplexed applications, the driver amplifier and the AD7942 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 14- bit level (0.006%). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at a 14-bit level and should be verified prior to driver selection. table 9. recommended driver amplifiers. amplifier typical application ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8605 , ad8615 5 v single-supply, low power ad8519 small, low power and low frequency ad8031 high frequency and low power voltage reference input the AD7942 voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins as explained in the layout section. when ref is driven by a very low impedance source, e.g., a reference buffer using the ad8031 or the ad8605 , a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, smaller reference decoupling capacitor values down to 2.2 f can be used with a minimal impact on performance, especially dnl.
prelim inary technical data AD7942 r e v pr b | pa ge 17 o f 28 power supply the AD7942 is s p ecif ie d o v er a wide o p era t in g ra n g e f r o m 2.3 v t o 5.5 v . i t has, unlik e o t her lo w v o l t a g e co n v e r t e rs, a n o is e lo w en o u g h t o desig n a lo w s u p p l y ( 2 .5v) 14-b i t r e s o l u tio n sys t em wi t h re sp e c t a bl e p e r f or manc e. i t u s e s two p o we r su p p ly p i ns : a c o re su p p ly v d d and a dig i t a l i n p u t / out p u t i n te r f ac e su p p ly vi o . vi o al lo ws dir e c t in t e r f ac e wi th an y log i c betw een 1.8 v a nd vdd . t o r e d u ce t h e sup p li es n e e d e d , t h e v i o an d vdd can be tied t o g e t h er . the AD7942 is indep e n d en t o f p o w e r s u p p l y s e q u e n cin g b e t w e e n v i o and vdd . a d d i t i o n a l ly , i t is ver y i n s e ns i t ive to p o we r supply v a r i a t i o ns ove r a w i d e f r e q u e nc y ra n g e , as sh o w n in f i gur e 26, w h ich r e p r es en ts ps rr o v er fr e q u e n c y . fi g u r e 2 6 . p s r r v s . fr e q u e n c y the AD7942 p o w e rs do wn a u t o ma tic a l l y a t t h e end o f eac h co n v ersio n phas e a n d , t h er efo r e , t h e p o w e r s c ales lin e a r l y wi t h th e s a m p lin g ra te as sh o w n in s e e f i gur e 27. this mak e s t h e p a r t ide a l f o r lo w s a m p lin g r a t e ( e ven a f e w h z ) and lo w ba t t er y- p o w e r e d ap p l i c at i o n s . f i gure 2 7 . o p er a t i n g c u rrents vs . s a mpl i n g r a te supplying the adc fro m th e referen c e f o r sim p lif i ed a p p l ica t io n s , the AD7942, wi th i t s lo w o p era t in g c u r r e n t , c a n b e supp l i e d d i re c t l y u s i n g t h e re f e re nc e c i rc u i t , a s sh own i n f i gur e 28. th e r e fer e nce line can b e d r i v en b y ei t h er : ? the s y ste m p o we r su p p ly dire c t ly ? a r e fer e n c e v o l t a g e wi t h e n o u g h c u r r en t o u t p ut ca p a b i li ty , s u c h as the ad r43x ? a r e f e r e n c e b u f f er , s u c h as th e ad8031, tha t c a n als o f i l t er t h e syst em p o w e r s u p p l y , as s h own in f i gu r e 28. ad8031 AD7942 vio ref vdd 10 f 1 f 10 ? 10k ? 5v 5v 5v 1 f (note 1) note 1: optional reference buffer and fil ter f i g u re 28. e x a m pl e of a p pl ic at io n ci r c uit
AD7942 preliminary technical data rev pr b | page 18 of 28 digital interface though the AD7942 has a reduced number of pins, it offers flexibility in its serial interface modes. the AD7942, when in cs mode, is compatible with spi, qspi, digital hosts, and dsps, e.g., blackfin? adsp-bf53x or adsp- 219x). this interface can use either 3-wire or 4-wire. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. the AD7942, when in chain mode, provides a daisy chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is always selected. in either mode, the AD7942 offers the flexibility to optionally force a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled as follows: ? in the cs mode, if cnv or sdi is low when the adc conversion ends (figure 32 and figure 36). ? in the chain mode, if sck is high during the cnv rising edge (figure 40).
prelim inary technical data AD7942 r e v pr b | pa ge 19 o f 28 cs mo de 3-wir e , no busy in dicator this m o de is us ual l y us ed w h en a sin g le ad794 2 is co nnec t e d t o a n s p i co m p a t ib le dig i tal h o s t . th e co nnec tio n dia g ram is sh own i n f i gur e 29 a nd t h e co r r esp o n d i n g t i m i n g is g i ven in f i gur e 30. w i t h s d i tie d to vi o , a r i sin g edg e o n c n v ini t ia t e s a co n v ersio n , s e le c t s th e cs m o de, and fo r c es s d o to hig h im p e d a n c e . o n ce a con v ersio n is ini t i a t e d , i t wi l l co n t i n ue t o co m p le ti o n i r r e s p ecti v e o f th e sta t e o f c n v . f o r i n s t a n ce , i t co u l d be us ef u l t o b r in g c n v l o w t o s e lec t o t her s p i de vices, s u c h a s a n a l o g mu l t i p l e x e r s , b u t c n v mu s t b e r e t u r n e d h i g h be f o r e th e m i nim u m co n v e r si o n tim e a n d h e ld h i gh un til t h e m a x i m u m c o n v e r s i on t i me to avoi d t h e ge ne r a t i on of t h e b u sy sig n al indic a t o r . w h en t h e con v ersio n is co m p l e t e , the AD7942 en t e rs t h e ac q u isi t io n phas e and p o w e rs do wn. w h en c n v g o e s lo w , t h e ms b is o u t p ut o n t o sd o . th e r e maini n g da t a b i ts a r e t h e n clo c k e d b y subs e q uen t s c k fa l l in g e d ges. the da t a is va li d on b o t h s c k e d ge s . a l t h ou g h t h e r i s i ng e d ge c a n b e u s e d to ca pt ur e t h e da t a , a dig i t a l h o st als o usin g t h e sc k fal l in g e d g e wi l l a l lo w a fa ster r e adin g ra t e p r o v ide d i t has a n acce p t a b le h o ld tim e . a f t e r th e 14th sc k falli n g ed g e o r w h en cn v g o e s hig h , w h ich e v e r is e a rlier , s d o r e t u r n s t o hig h i m p e dance . cnv sck sdo sdi data in clk convert v io digit al host AD7942 f i g u re 29. cs mode 3-w i r e , n o b u sy ind i c a tor c o nne c t ion d i agr a m (sdi high) 04656-p r c-008 sdo d13 d12 d11 d1 d0 t dis sck 1 2 3 12 13 14 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition s di = 1 t cnvh t acq t en f i g u re 30. cs mode 3-w i r e , n o b u sy ind i c a tor s e ri al inte r f a c e ti ming (s di hig h )
AD7942 prelim inary technical data r e v pr b | pa ge 20 o f 28 cs mode 3-wir e with busy in dicator this m o de is us ual l y us ed w h en a sin g le ad794 2 is co nnec t e d t o a n s p i co m p a t ib le dig i tal h o s t ha vin g an in ter r u p t in p u t. the co n n e c t i on di a g r a m is sh ow n in f i gur e 31 a nd t h e co r r es p o n d in g t i min g is g i v e n in f i gur e 32. w i t h s d i tie d to vi o , a r i sin g edg e o n c n v ini t ia t e s a co n v ersio n , s e le c t s th e cs m o de, and fo r c es s d o to hig h im p e d a n c e . s d o is ma i n t a i n e d in hig h i m p e dan c e u n t i l t h e c o m p l e t i on of t h e c o n v e r s i o n i r re sp e c t i ve of t h e st ate of c n v . pr io r to t h e min i m u m con v ersio n t i m e , c n v cou l d b e us e d to s e lec t o t h e r s p i de vices, s u c h as a n alog m u l t i p lexers, b u t cnv m u s t be r e t u r n e d lo w be f o r e th e mini m u m con v ersio n t i m e and h e l d lo w un t i l t h e maxim u m c o n v ersio n t i m e t o gua r a n t e e t h e g e n e r a t i o n o f t h e b u s y sig n al i n dic a t o r . w h en t h e con v ersio n i s co m p let e , sd o g o es f r o m hig h im p e dan c e t o lo w . w i t h a p u l l - u p o n th e s d o li n e , th i s tra n si tio n ca n be used a s a n in t e rr u p t s i g n a l to i n i t i a te t h e d a t a re a d i n g co n t r o l l ed b y th e dig i t a l h o st. the AD7942 then en t e rs the ac q u isi t io n p h as e a nd p o w e rs do wn. the da t a b i ts a r e t h en clo c k e d o u t, ms b f i rs t, b y s u b s eq u e n t sc k f a l l i n g ed g e s . t h e d a ta i s v a l i d o n b o t h sc k e d g e s. a l t h o u g h th e r i sin g e d ge ca n be us e d t o c a p t ur e the da t a , a d i g i tal h o s t als o usi n g th e sck falli n g ed g e will allo w a fa s t e r r e adin g ra t e p r o v ide d i t has an a c cep t a b le h o ld t i me . af t e r t h e opt i on a l 1 5 t h s c k f a l l i n g e d ge, or w h e n c n v go e s h i g h , w h iche v e r is e a rlier , s d o r e t u r n s t o hig h i m p e d a n c e . cnv sck sdo sdi data in irq clk convert v io vio digit al host AD7942 47k ? f i g u re 31. cs mode 3-w i r e with b u sy i n d i c a to r c o nne c t ion d i agr a m (sdi high) 04656-p r c-010 sdo d13 d12 d1 d0 t dis sck 1 2 3 13 14 15 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc t cnvh t acq acquisition sdi = 1 f i g u re 32. cs m o d e 3 - wi re w i t h bus y i n d i ca to r s e r i a l i n te r f a c e t i m i n g ( s d i h i g h )
prelim inary technical data AD7942 r e v pr b | pa ge 21 o f 28 cs mode 4-wir e , no busy in dic a tor this m o de is us ual l y us ed w h en m u l t i p le ad79 42s a r e co nnec t e d t o an s p i co m p a t ib le dig i tal h o st. a co nn ec tion dia g ra m exam p l e usin g tw o ad7 942s is s h own in f i gur e 33 a nd t h e co r r es p o n d in g timin g is g i ven in f i gur e 34. w i t h s d i hig h , a r i sin g edg e on cnv ini t ia t e s a co n v ersio n , se l e ct s t h e cs m o d e , a nd fo r c es s d o to hig h im p e dan c e. i n t h is m o de , cnv m u s t b e h e ld hig h d u r i n g t h e con v ersio n phas e and th e su b s e q ue n t da ta r e ad ba ck (if s d i a n d c n v a r e lo w , s d o i s dr i v en lo w). pr i o r to t h e mi ni m u m con v ersio n t i me, s d i co u l d be us e d t o s e lec t o t h e r s p i de vices, s u c h as a n al og m u l t i p lexers, b u t s d i m u s t b e r e t u r n e d hig h bef o r e the minim u m con v ersion t i me an d held h i g h un t i l t h e ma x i m u m con v ersi o n t i m e to a v o i d t h e gener a t i o n o f t h e b u s y sig n a l i ndic a to r . w h e n t h e co n v ersio n is com p let e , t h e AD7942 en t e rs t h e acq u isi t ion p h as e a nd p o w e rs do w n . e a ch a d c r e su l t ca n b e r e ad b y b r in g i n g lo w it s sdi i n pu t w h i c h c o n s e q u e nt l y output s t h e m s b on to s d o . the r e ma in in g d a t a b i ts a r e t h e n clo c k e d b y subs e q ue n t sc k dr i v i n g e d ges. t h e d a t a is va lid o n b o t h sc k e d ges. a l t h o u g h th e n o n d ri v i n g ed g e ca n be use d t o ca p t ur e th e da ta , a d i g i tal h o s t als o usin g t h e sc k fal l ing e d g e wil l al lo w a fas t er r e adin g ra t e p r o v ided i t has a n accep t able h o ld time . af ter th e 14th s c k fa l l in g e d ge , o r w h en s d i go e s hig h , w h ich e v e r is e a rlier , s d o r e t u r n s to hig h i m p e dance and a n o t h e r ad794 2 ca n b e r e a d . cnv sck sdo sdi data in clk cs1 convert cs2 digit al host AD7942 cnv sck sdo sdi AD7942 f i g u re 33. cs mo de 4 - w i r e , no b u sy ind i c a to r c o nnectio n di a g r a m 04656-p r c-012 sdo d13 d12 d11 d1 d0 t dis sck 12 3 2 6 2 7 2 8 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 12 13 t sck t sckl t sckh d0 d13 d12 15 16 14 sdi(cs2) f i g u re 34. cs mode 4-w i r e , n o b u sy ind i c a tor s e ri al inte r f a c e ti ming
AD7942 prelim inary technical data r e v pr b | pa ge 22 o f 28 cs mode 4-wir e with busy in dicator this m o de is us ual l y us ed w h en a sin g le ad794 2 is co nnec t e d t o a n s p i co m p a t ib le d i g i t a l h o st, w h ich has a n in t e r r u p t in p u t, a nd i t is desir e d t o k e ep c n v , w h ic h is us ed t o s a m p le t h e a n alog in p u t, indep e n d en t o f t h e sig n al us ed t o s e lec t t h e da ta r e ading. this r e q u ir em e n t is p a r t ic u l a r ly im p o r t a n t in a p plic a t ion s w h er e lo w ji t t e r o n cnv is desir e d. the co n n e c t i on di a g r a m is sh ow n in f i gur e 35 a nd t h e co r r es p o n d in g t i min g is g i v e n in f i gur e 36. w i t h s d i hig h , a r i sin g edg e on cnv ini t ia t e s a co n v ersio n , se l e ct s t h e cs m o d e , a nd fo r c es s d o to hig h im p e dan c e. i n t h is m o de , cnv m u s t b e h e ld hig h d u r i n g t h e con v ersio n phas e and th e su bs e q uen t da ta r e ad back (if s d i a nd cnv a r e lo w , s d o is dr i v en lo w). pr i o r to t h e mi ni m u m con v ersio n t i me, s d i co u l d be us e d t o s e lec t o t h e r s p i de vices, s u c h as a n al og m u l t i p lexers, b u t s d i m u s t b e r e t u r n e d lo w bef o r e the minim u m con v ersion ti m e a n d h e ld lo w un til th e m a xi m u m co n v e r sio n tim e t o g u ar an t e e t h e g e ne r a t i on of t h e b u sy s i g n a l i n d i c a tor . whe n t h e con v ersio n i s co m p let e , sd o g o es f r o m hig h im p e dan c e t o lo w . w i th a p u ll- u p o n t h e s d o li n e , th i s tra n si t i o n ca n be use d as a n i n ter r u p t sig n a l t o ini t i a te t h e da t a r e a d b a ck co n t r o l l e d b y th e dig i t a l h o st. the AD7942 then en t e rs the ac q u isi t io n p h as e a nd p o w e rs do w n . t h e da t a b i t s a r e t h e n clo c k e d o u t, msb f i rst, b y subs e q ue n t s c k dr ivin g e d ges. th e d a t a is v a lid o n b o t h sc k ed g e s . al t h o u gh th e ri s i n g ed g e ca n be use d t o ca p t ur e th e da ta , a d i g i tal h o s t also usi n g th e sc k fallin g edg e w i ll allo w a fas t er r e adin g ra t e p r o v ide d i t has a n ac cep t ab le h o ld time . af t e r th e o p ti o n al 15t h sc k fallin g e d g e , o r s d i g o i n g h i gh , w h iche v e r is e a rlier , t h e s d o r e t u r n s t o hig h i m p e dan c e . cnv sck sdo sdi data in irq clk convert cs1 vio digit al host AD7942 47k ? f i g u re 35. cs mode 4- w i r e with b u sy i n d i c a tor conne c t ion d i agr a m 04656-p r c-014 sdo d13 d12 d1 d0 t dis sck 1 2 3 13 14 15 t sck t sckl t sckh t hsdo t dsdo t en conversion a cquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv f i g u re 36. cs mode 4-w i r e with b u sy i n d i c a to r s e r i a l in ter f a c e ti ming
prelim inary technical data AD7942 r e v pr b | pa ge 23 o f 28 c h ain mo de, no bu sy in dic a tor this m o de can be us e d t o da isy c h a i n m u l t i p le AD7942s o n a 3 - wir e s e r i al in t e r f ace . this f e a t ure is us ef u l f o r r e d u cin g co m p on e n t co u n t and w i r i n g c o nn e c t i o n s, e. g., in is ol a t e d m u l t icon v e r t er a p plic a t ion s o r fo r sy st em s wi t h a limi t e d in t e r f acing c a p a ci ty . d a t a r e a d b a ck is a n a l ogo u s t o clo c k i n g a shif t re g i s t e r . a co nn ec tion dia g ra m exam p l e usin g tw o ad7 942s is s h own in f i gur e 37 a nd t h e co r r es p o n d in g timin g is g i ven in f i gur e 38. w h en s d i a nd cnv a r e lo w , sd o is dr i v en low . w i t h sc k lo w , a r i sin g e d g e on cnv ini t ia t e s a co n v ersio n , s e le c t s the c h a i n m o de , a n d d i sa b l es th e b u s y in di ca t o r . i n th i s m o de , cnv i s h e l d hig h d u r i ng th e con v ersion p h as e an d t h e s u bs e q uen t da t a r e ad b a ck. w h en t h e con v ersio n is co m p let e , t h e ms b is o u t p u t o n t o s d o an d t h e AD7942 en t e rs th e acq u is i t ion p has e an d po w e r s d o w n . th e r e m a i n in g da ta b i t s st o r ed in th e i n t e rn al s h i f t r e gi s t e r a r e th en c l oc k e d b y s u b s eq uen t sc k fall i n g ed g e s . f o r e a ch ad c, s d i fe e d s t h e in p u t o f t h e in ter n a l shif t r e g i st er a nd is clo c k e d b y t h e sc k fa l l ing e d ge . e a ch a d c in t h e cha i n o u t p u t s i t s da t a ms b f i rs t, an d 1 4 n c l o c ks a r e r e q u ir e d t o r e ad b a ck t h e n ad cs. the da t a is valid o n b o t h sck e d g e s. al th o u g h th e ri si n g ed g e ca n b e used t o ca p t ur e th e da t a , a dig i t a l h o st a l s o usin g t h e sc k f a l l in g e d ge w i l l a l lo w a fast er r e adin g ra t e and , co n s e q uen t l y m o r e AD7942s in t h e c h a i n, prov i d e d t h e d i g i t a l ho s t h a s an a c c e pt a b l e ho l d t i m e . t h e maxim u m con v ersio n ra t e ma y b e r e d u ce d d u e t o t h e t o t a l r e a d ba ck tim e . f o r i n s t a n ce , w i th a 5 n s d i gi tal h o s t set - u p tim e a nd 3 v in t e r f ac e , u p t o six ad7 942s r u nnin g a t a co n v ersio n ra t e o f 250 ks ps ca n be da isy-c h a i ned on a 3 - wir e p o r t . cnv sck sdo sdi clk convert data in digit al host AD7942 b cnv sck sdo sdi AD7942 a f i gure 37. chain m o de , n o b u sy ind i c a tor conne c t ion d i agr a m 04656-p r c-016 sdo a = sdi b d a 13 d a 12 d a 11 sck 12 3 2 6 2 7 2 8 t ssdisck t hsdisc t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 12 13 t sck t sckl t sckh d a 0 15 16 14 sdi a = 0 sdo b d b 13 d b 12 d b 11 d a 1 d b 1d b 0d a 13 d a 12 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 f i gure 38. cha i n m o de , n o b u sy ind i c a to r s e r i a l in ter f ace tim i ng
AD7942 prelim inary technical data r e v pr b | pa ge 24 o f 28 c h ain mo de w i th bu sy in dic a tor this m o de can als o be us ed t o da isy c h ain m u l t i p le AD7942s on a 3-w i r e se rial in t e rfa c e wh ile p r o v i d i n g a b u s y in d i ca t o r . t h is f e a t ur e is us ef u l f o r r e d u cin g co m p on en t co u n t a nd wir i n g co nne c t io n s , e . g . , in is ol a t e d m u l t ico n ver t er a p plica t ion s o r fo r syst em s wi t h a l i mi te d in ter f acin g ca p a c i ty . d a t a r e ad b a ck is a n alog o u s t o c l oc ki n g a s h i f t r e gi s t er . a co nn ec tion dia g ra m exam p l e usin g thr e e AD7942s is s h own in f i gur e 39 and t h e co r r esp o ndin g t i min g is g i ven i n f i gur e 4 0 . w h en s d i a nd cnv a r e lo w , s d o is dr i v en low . w i th sc k hig h , a r i sin g e d g e on cnv ini t ia t e s a co n v ersio n , s e le c t s the c h a i n m o d e , an d en a b les t h e b u s y i ndic a to r fe a t ur e. i n t h is m o d e , cnv is he ld hig h d u r i n g t h e con v ersio n phas e a nd t h e s u bs e q uen t da t a r e ad back. w h en al l ad cs in t h e c h ain ha v e co m p let e d t h eir co n v ersio n s, t h e n e a r end ad c ( ad c c in f i gur e 39) s d o wil l be dr i v en hig h . this tran si t i o n o n s d o ca n b e us e d as a b u s y i n di c a t o r t o t r ig ger t h e da t a r e ad b a ck co n t r o l l ed b y the dig i tal h o s t . th e AD7942 t h en en t e rs the acq u isi t ion pha s e an d p o w e rs do wn. t h e d a t a b i ts sto r e d i n t h e in t e r n a l shif t r e g i st er a r e t h e n clo c k e d o u t, msb f i rst, b y s u b s e q ue n t sck fall i n g e d g e s . f o r ea c h a d c , s d i f eed s th e in p u t o f t h e i n t e r n a l shif t r e g i st e r a n d is clo c k e d b y t h e sc k fal l in g edge . e a c h ad c in the cha i n o u t p u t s i t s da ta m s b f i rs t, a nd 14 n + 1 c l o c ks a r e r e q u ir ed t o r e ad b a c k th e n ad cs. al th o u g h th e ri si n g ed g e ca n b e used t o ca p t ur e th e da t a , a dig i t a l h o st a l s o usin g t h e sc k f a l l in g e d ge w i l l a l lo w a fast er r e adin g ra t e and , co n s e q uen t l y m o r e AD7942s in t h e c h a i n, p r o v ided t h e dig i tal h o s t has a n accep t ab le h o l d time . f o r in st an c e , w i t h a 5 n s dig i t a l h o st s e t-u p t i me and 3 v in t e r f ace, u p t o six ad79 42s r u nnin g a t a co n v ersio n r a t e o f 250 ks ps can b e da isy - cha i n e d to a sin g le 3 - wir e p o r t . cnv sck sdo sdi clk convert data in irq digit al host AD7942 c cnv sck sdo sdi AD7942 b cnv sck sdo sdi AD7942 a f i gure 39. chain m o de with b u sy i n dic a tor c o nn ec tion d i agr a m 04656-p r c-018 sdo a = sdi b d a 13 d a 12 d a 11 sck 12 3 35 41 42 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 41 3 t sck t sckh t sckl d a 0 15 31 13 sdo b = sdi c d b 13 d b 12 d b 11 d a 1 d b 1d b 0d a 13 d a 12 43 t ssdisck t hsdisc t hsdo t dsdo sdo c d c 13 d c 12 d c 11 d a 1d a 0 d c 1d c 0d a 12 17 27 28 16 29 d b 1d b 0d a 13 d b 13 d b 12 t dsdosdi t ssckcnv t hsckcnv d a 0 f i gure 40. cha i n m o de with b u sy i n di c a tor s e ri al inte r f a c e ti ming
prelim inary technical data AD7942 r e v pr b | pa ge 25 o f 28 appli c a t ion hints la y o u t the p r in te d cir c ui t b o a r d t h a t ho us es t h e ad79 42 s h o u ld b e desig n e d s o t h a t t h e a n a l o g a nd dig i t a l s e c t io n s a r e s e p a r a te d a nd co nf i n e d to cer t a i n a r e a s o f t h e b o a r d . t h e p i n o u t o f t h e AD7942 wi t h al l i t s a n alog sig n als o n th e lef t side an d al l i t s dig i t a l sig n als o n the r i g h t side e a s e s this tas k . a v o i d r u nnin g dig i t a l li n e s u n der t h e de vice b e ca us e t h es e co u p le n o is e o n to t h e die, un less a g r o u nd plane un d e r t h e AD7942 is us ed as a s h ie ld . f a s t swi t c h in g sig n a l s, s u c h as cnv o r c l o c ks, s h o u l d n e v e r r u n n e ar a n alog sig n al p a th s. cr os s o v e r of d i g i t a l a n d a n a l o g s i g n a l s sh ou l d b e a v oi d e d a t leas t on e g r oun d plan e s h o u l d b e us ed . i t cou l d be comm o n o r spli t b e twe e n t h e dig i t a l an d a n a l og s e c t io n. i n such a ca s e , i t s h o u ld b e jo in e d under n e a th t h e AD7942s. the AD7942 v o l t a g e r e f e r e nce in p u t ref has a d y na mic in p u t im p e d a n c e and sh o u ld b e de cou p le d wi t h min i ma l p a r a si t i c ind u c t an ces. th a t is don e b y pl a c in g t h e r e fer e nce de co u p li n g c e r a m i c c a p a c i t o r cl o s e to , and i d e a l l y r i g h t up ag ai ns t , t h e r e f a nd g n d p i n s a nd co n n e c t t h e s e p i n s w i t h wid e , lo w im p e d a n c e t r ac es. f i nal l y , th e p o wer s u p p l y vd d a nd vi o o f t h e AD7942 sh o u ld be deco u p led wi th ceramic c a p a ci t o rs, typ i cal l y 100 nf , p l aced c l os e t o th e AD7942 a nd co nn e c t e d usin g sh o r t a nd la rg e traces t o p r o v ide lo w im p e dance p a t h s a nd r e d u c e t h e ef fe c t o f g l i t ches on t h e p o we r sup p ly l i ne s . an exa m ple o f l a yo u t fol l o w in g t h es e r u les is s h o w n i n f i gur e 41 a nd f i gur e 4 2 . ev al u a ting the ad79 42 s performance o t h e r r e co mm en de d l a yo u t s f o r th e AD7942 a r e o u tlined in t h e eval ua tion bo a r d f o r th e ad794 2 ( ev a l - a d 7 9 4 2 ). t h e e v a l ua t i on b o a r d p a ck a g e i n cl u d es a f u l l y ass e m b le d and teste d e v a l ua t i on b o a r d , do c u m e n t a t i o n, a nd s o f t wa re fo r co n t r o l l in g t h e b o a r d f r o m a pc vi a t h e ev a l - c on trol br d 2 . f i g u re 41. e x a m pl e of layo ut of t h e a d 79 42 ( t op l a yer) f i g u re 42. e x a m pl e of layo ut of t h e a d 79 42 (bot t o m laye r)
AD7942 prelim inary technical data r e v pr b | pa ge 26 o f 28 outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba f i g u re 43. 10-l e ad m i cro s m al l o u t l in e p a ckag e [m s o p ] (r m - 10) di me nsio ns sho w n i n mi ll im e t e r s 3.00 bsc sq index area top view 1.50 bcs sq exposed pad (b o t t o m view) 1.74 1.64 1.49 2.48 2.38 2.23 5 10 6 0.50 bsc 0.50 0.40 0.30 0.80 0.75 0.70 0.05 max 0.02 nom s eating plane 0.30 0.23 0.18 0.20 ref 0.80 max 0.55 typ 1 pin 1 indicator paddle connected to gnd. this connection is not required to meet the electrical performances f i gure 44. 1 0 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [ qfn (lfcsp )] 3 mm 3 m m b o d y (c p - 1 0 ) di me nsio ns sho w n i n mi ll im e t e r s
preliminary technical data AD7942 rev pr b | page 27 of 28 ordering guide models temperature range package (option) transport media, quantity brand AD7942brm C40c to +85c msop (rm-10) tube, 50 c1n AD7942brmrl7 C40c to +85c msop (rm-10) reel, 1,000 c1n AD7942bcpwp C40c to +85c qfn [lfcsp] (cp-10) waffle pack, 50 c1n AD7942bcprl7 C40c to +85c qfn [lfcsp] (cp-10) reel, 1,500 c1n eval-AD7942cb 6 evaluation board eval-control brd2 7 controller board eval-control brd3 2 controller board 6 this board can be used as a standalone evaluation board or in conjunction with the eval-control brdx for evaluation/demonstrat ion purposes. 7 these boards allow a pc to control and communicate with all analog devices evaluation boards ending in the cb designators.
AD7942 prelim inary technical data r e v pr b | pa ge 28 o f 28 notes ? 2004 a n al og devic e s , inc . a ll rig h t s r e ser v e d . t r a d em arks an d r e gist er e d tr adem ar ks ar e t h e proper t y of t h eir respec tiv e o w ners .

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